
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:46:03 03/10/2012
-- Design Name:   DataMemory
-- Module Name:   C:/Prog/CUARTO/AIC/CycloneProject/procesadorcyclone-aic-uspceu-2011-2012/ES/tb_DataMemory.vhd
-- Project Name:  entradaSalida
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: DataMemory
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_DataMemory_vhd IS
END tb_DataMemory_vhd;

ARCHITECTURE behavior OF tb_DataMemory_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT DataMemory
	PORT(
		data_word_i : IN std_logic_vector(7 downto 0);
		data_addr_i : IN std_logic_vector(7 downto 0);
		rw : IN std_logic;
		data_cyc_i : IN std_logic;
		data_stb_i : IN std_logic;          
		data_ack_o : OUT std_logic;
		data_word_o : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL rw :  std_logic := '0';
	SIGNAL data_cyc_i :  std_logic := '0';
	SIGNAL data_stb_i :  std_logic := '0';
	SIGNAL data_word_i :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL data_addr_i :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL data_ack_o :  std_logic;
	SIGNAL data_word_o :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: DataMemory PORT MAP(
		data_word_i => data_word_i,
		data_addr_i => data_addr_i,
		rw => rw,
		data_cyc_i => data_cyc_i,
		data_stb_i => data_stb_i,
		data_ack_o => data_ack_o,
		data_word_o => data_word_o
	);

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
		-- Escritura pos 001
		rw <= '1';
		data_addr_i <= x"01";
		data_word_i <= "00000011";
		wait for 10 ns;
		data_cyc_i <= '1';
		data_stb_i <= '1';
		wait for 100 ns;
		data_cyc_i <= '0';
		data_stb_i <= '0';
		wait for 100 ns;
		
		-- Escritura pos 002
		rw <= '1';
		data_addr_i <= x"02";
		data_word_i <= "00000111";
		wait for 10 ns;
		data_cyc_i <= '1';
		data_stb_i <= '1';
		wait for 100 ns;
		data_cyc_i <= '0';
		data_stb_i <= '0';
		wait for 100 ns;
		
		-- Lectura pos 001
		rw <= '0';
		data_addr_i <= x"01";
		wait for 10 ns;
		data_cyc_i <= '1';
		data_stb_i <= '1';
		wait for 100 ns;
		data_cyc_i <= '0';
		data_stb_i <= '0';
		wait for 100 ns;
		
		-- Escritura pos 002
		rw <= '1';
		data_addr_i <= x"02";
		data_word_i <= "00011011";
		wait for 10 ns;
		data_cyc_i <= '1';
		data_stb_i <= '1';
		wait for 100 ns;
		
		-- Lectura pos 002
		rw <= '0';
		data_addr_i <= x"02";
		wait for 100 ns;
		data_cyc_i <= '0';
		data_stb_i <= '0';
		
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
